The present invention relates to an interconnect structure for an integrated circuit and to a corresponding fabrication method.
Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to the bit lines of integrated memory circuits using silicon technology.
In integrated semiconductor memory circuits, the individual memory cells are usually arranged in matrix form and connected to word lines running in a first direction and bit lines running perpendicularly thereto in a second direction. The addressing is effected by activation of the desired word line and the bit selection by activation of a relevant bit line.
A critical factor for the speed of the information transfer in such integrated memory circuits is the coupling capacitance between the individual bit lines. In particular, if such a coupling capacitance is high, it causes signal distortions, signal attenuations and crosstalk. In customary integrated memory circuits, in which the bit lines all lie in a single interconnect plane, so-called bit line entanglement is employed in order to reduce the signal coupling caused by the coupling capacitances.
A further possibility for reducing the coupling capacitances is to increase the distance between the individual bit lines by reducing the width/distance ratio. This possibility of improvement is limited, however, by the rise in resistance which is brought about by the narrowing of the bit lines.
Therefore, it is an object of the present invention to provide an improved interconnect structure for an integrated circuit and a corresponding fabrication method which has a lower coupling capacitance between adjacent interconnects.
According to the invention, this object is achieved by means of the interconnect structure for an integrated circuit according to claim 1.
The idea on which the present invention is based consists in dividing the individual interconnects of an interconnect structure of at least two interconnects into sections which lie in different interconnect planes. Thus, in the case of the interconnect structure according to the invention, a second interconnect plane is introduced which makes it possible to shift adjacent interconnect sections of the bit lines in a matrix vertically with respect to one another, in order thus to reduce the coupling capacitances through the distance that is increased in sections.
In this case, in particular, a first and second interconnect are offset with respect to one another in the longitudinal direction in such a way that the interconnect sections of the first interconnect which lie in the first interconnect plane run at least in sections beside the interconnect sections of the second interconnect which lie in the second interconnect plane, and that the interconnect sections of the first interconnect which lie in the second interconnect plane run at least in sections beside the interconnect sections of the second interconnect which lie in the first interconnect plane.
The subject-matters according to the invention have the advantage, inter alia, over the known solution approaches that the disturbing coupling capacitances can be significantly reduced.
Advantageous developments and improvements of the respective subject-matter of the invention can be found in the subclaims.
In accordance with one preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the first interconnect plane are in each case directly connected, one to the other, to the interconnect sections of the first interconnect and, respectively, the interconnect sections of the second interconnect which lie in the second interconnect plane.
In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the first interconnect plane are preferably connected in their ends or in their center via respective first contacts to terminals integrated underneath.
In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the second interconnect plane are preferably connected in their center via respective second contacts to terminals integrated underneath.
In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect all have an identical length.
In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect are offset with respect to one another approximately by the length or approximately by half the length.
In accordance with a further preferred development, a multiplicity of first and second interconnects arranged parallel to one another are provided, which are offset with respect to one another in a regular pattern.
In accordance with a further preferred development, the multiplicity of first and second interconnects arranged parallel to one another are bit lines of an integrated memory circuit.
Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description below.